1. Field of the Invention
The present invention relates to a differential amplifier and a method of compensation, and more particularly it relates to a differential amplifier that is suitable for use in the pre-amplifier of an audio amplifier.
2. Description of the Related Art
A known fully differential amplifier is as shown in FIG. 2 (for example as in Okamoto, T. et al, "A 16b Oversampling CODEC with filtering DSP", ISSCC Dig. Tech. Papers, pp 74-77, Feb. 1991).
The fully differential amplifier of the past as shown in FIG. 2 is formed by a first MOSFET of a first polarity (MP1), the gate of which is connected to a non-inverting input terminal (103), a second MOSFET of the first polarity (MP2), the gate of which is connected to an inverting input terminal (104) and the source of which is connected to the source of MP1, a third MOSFET of the first polarity (MP3), the source of which is connected to a first power supply (101) and the drain of which is connected to the source of MP1, a fifth MOSFET of the first polarity (MP5), the source of which is connected to the first power supply (101) and the gate of which is connected to the drain of MP5, a sixth MOSFET of the first polarity (MP6), the source of which is connected to the first power supply (101), the gate of which is connected to the gate of MP5, and the drain of which is connected to a non-inverting output terminal (105), a seventh MOSFET of the first polarity (MP7), the gate of which is connected to the non-inverting input terminal (103), an eighth MOSFET of the first polarity (MP8), the gate of which is connected to the inverting input terminal (104) and the source of which is connected to the source of MP7, a ninth MOSFET of the first polarity (MP9), the drain of which is connected to the source of MP7 and the gate of which is connected to the common-mode feedback input terminal (107), an eleventh MOSFET of the first polarity (MP11), the source of which is connected to the first power supply (101) and the gate of which is connected to the drain of MP11, a twelfth MOSFET of the first polarity (MP12), the source of which is connected to the first power supply (101), the gate of which is connected to the gate of MP11, and the drain of which is connected to the non-inverting output terminal (106), a thirteenth MOSFET of the first polarity (MP13), the source of which is connected to the first power supply (101) and the gate and the drain of which is connected to the gate of MP3, a first MOSFET of a second polarity (MN1), the source of which is connected to a second power supply (102), and the gate and drain of which are connected to the drain of MP7, a second MOSFET of the second polarity (MN2), the source of which is connected to the second power supply, the gate of which is connected to the drain of MN1, and the drain of which is connected to the drain of MP2, a third MOSFET of the second polarity (MN3), the source of which is connected to the second power supply (102), the gate of which is connected to the gate and drain of MN1, and the drain of which is connected to the drain of MP5, a sixth MOSFET of the second polarity (MN6), the source of which is connected to the second power supply (102), the gate of which is connected to the drain of MN2, and the drain of which is connected to the drain of MP6, a seventh MOSFET of the second polarity (MN7), the source of which is connected to the second power supply (102), and the gate and the drain of which are connected to the drain of MP8, an eighth MOSFET of the second polarity (MN8), the source of which is connected to the second power supply (102), the gate of which is connected to the gate and the drain of MN7, and the drain of which is connected to the drain of MP1, a ninth MOSFET of the second polarity (MN9), the source of which is connected to the second power supply (102), the gate of which is connected to the gate and the drain of MN7, and the drain of which is connected to the drain of MP11, a twelfth MOSFET of the second polarity (MN12), the source of which is connected to the second power supply (102), the gate of which is connected to the drain of MN8, and the drain of which is connected to the drain of MP12, a thirteenth MOSFET of the second polarity (MN13), the source of which is connected to the second power supply (102), the gate and the drain of which are connected to one end of a constant-current power supply (108), and a fourteenth MOSFET of the second polarity (MN14), the source of which is connected to the second power supply (102), the gate of which is connected to the gate and the drain of MN13, and the drain of which is connected to the drain of MP13. In addition to the above-described MOSFETs, this circuit has a constant-current power supply (108), one end of which is connected to the first power supply (101), and the other end of which is connected to the drain of MN13, a first resistor (R1), one end of which is connected to the gate of MN6, a first capacitor (C1), one end of which is connected to the inverting output terminal (105) and the other end of which is connected to the other end of the first resistor (R1), a second resistor (R2), one end of which is connected to the gate of MN12, a second capacitor (C2), one end of which is connected to the non-inverting output terminal (106) and the other end of which is connected to the other end of the second resistor (R2), a third resistor (R3), one end of which is connected to the gate of MN3, a third capacitor (C3), one end of which is connected to the drain of MP5, and the other end of which is connected to the other end of the third resistor (R3), a fourth resistor (R4), one end of which is connected to the gate of MN7, and a fourth capacitor (C4) one end of which is connected to the drain of MN9, and the other end of which is connected to the other end of the fourth resistor (R4).
The operation of the above-noted fully differential amplifier will be described with reference to FIG. 2. Because this amplifier is a fully differential amplifier, the description will be divided between the inverting output circuit section and the non-inverting output circuit section. First, referring to the inverting output circuit section, the constant-current transistor MP3, the differential input pair MP1, MP2, MP7 and MP2 and the load transistors MN1 and MN2 form a differential input gain stage, the non-inverting output signal of which is transmitted to the gate of MN6 and the inverting output signal of which is transmitted to the gate of MP6 via the inverting signal transmitting circuit formed by MOSFETs MN3 and MP5, thereby forming a two-stage push-pull output amplifier.
The desired phase margin is achieved by addition of the first compensation circuit that is formed by R1 and C1 between the drain of MP2 and the non-inverting output terminal (105), and by addition of the second compensation circuit formed by R3 and C3 between the inverting output of the differential input stage and the output of the inverting signal transmitting circuit. In the same manner with regard to the non-inverting output as well, the constant-current transistor MP3, the differential input pair MP1, MP2, MP8 and MP1 and the load transistors MN7 and MN8 form a differential input gain stage, the non-inverting output signal of which is transmitted to the gate of the MN12, and the inverting output signal of which is transmitted to the gate of MP12 via the inverting signal transmitting circuit formed by MOSFETs MN9 and MP11, thereby forming a two-stage push-pull output amplifier. The desired phase margin is achieved by addition of a compensation circuit that is formed by R2 and C2 between the non-inverting output of the differential input stage and the output of the drive stage, and by addition of a compensation circuit formed by R4 and C4 between the inverting output of the differential input stage and the output of the inverting signal transmitting circuit. And by applying a common mode feedback signal to the gate of MP9, the bias is stabilized.
In the above-noted prior art, however, the following problem exists. If we consider the pole frequencies of a two-stage CMOS amplifier, in view of the small-signal equivalent circuit of FIG. 3, from page 549 of P. R. Gray, and R. G. Meyer "Analysis and Design of Analog Integrated Circuits" Second Edition (published by JHON WILEY & SONS), these can be approximated as follows. EQU P1=-1/{(1+gm.sub.2 R.sub.2)C.sub.c R.sub.1 } (1) EQU P2=-gm.sub.2 C.sub.c /(C.sub.2 C.sub.1 +C.sub.2 C.sub.c +C.sub.c C.sub.1) (2)
In the above, P1 is frequency of the first pole, P2 is frequency of the second pole, gm.sub.2 is transconductance of the drive stage, C.sub.c is the compensation capacitance, C.sub.1 is the internal parasitic capacitance, and C.sub.2 is the load capacitance. To achieve phase margin, it is necessary to make P2 high with respect to frequency at which the gain is 1(.omega..sub.1 =gm.sub.1 /C.sub.c). As can be seen, however, from Equation (2), as the internal parasitic capacitance C.sub.1 becomes large, P2 becomes small, thereby reducing the phase margin of the two-stage amplifier.
At the inverting output terminal (105) side of the fully differential amplifier that is shown in FIG. 2, the internal parasitic capacitance C.sub.1 is chiefly either the sum of the gate capacitances of MN1, MN2, and MN3 and the drain capacitances of MP7, MN1, or the sum of the drain capacitances of MP2 and MN2 and the gate capacitance of MN6, whichever is larger. Normally, the latter is the governing factor and in particular in the case of an operational amplifier that is used in audio applications, because it is necessary, for the purpose of suppressing 1/f noise in the MOS transistors, to make the gate areas of MP1, MP2, MP7, MP8, MN1, MN2, MN7, and MN8 large, C.sub.1 becomes large. For this reason, because there was a significant reduction in the phase margin, to alleviate this problem of reduced phase margin, it was necessary to add the second compensation circuit for the inverting signal transmitting circuit, formed by R3 and C3. In the same manner, at the non-inverting output terminal side, it was necessary to add a compensation circuit for the inverting signal transmitting circuit, formed by R4 and C4.